There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This phenomenon is known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections of the IC (e.g., metal lines).
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information
In order to reduce capacitive coupling and therefore reduce capacitive crosstalk, low dielectric constant (low-K) materials have been developed to replace conventional dielectric/insulative materials that lie between conductive lines in order to insulate one conductive line from the other. Conventional insulative materials such as silicon dioxide exhibit a dielectric constant of about 4.0. Newer materials with lower dielectric constants have been developed. For example, polyimides generally exhibit a dielectric constant of about 2.4 to about 3.0; Teflon exhibits a dielectric constant of about 1.6 to 2.2; and aerogels typically exhibit a dielectric constant of about 2. However, the use of many low-K dielectric/insulative materials is not practicable because equipment is not available to properly process the new dielectric/insulative materials in various ICs. Furthermore, the chemical or physical properties of many low-K dielectric/insulative materials are usually difficult to make compatible or integrate into conventional IC processing.
FIG. 1 illustrates a portion of a conventional semiconductor fabrication process. An insulating layer is formed on a semiconductor substrate, both the insulating layer and substrate are generally indicated at 20. A conductive pattern 22 including conductive lines 24 is formed over the insulating/substrate layer 20. The conductive lines 24 are separated by interwiring spaces 26 formed on the insulating/substrate layer 20. A dielectric material such as silicon dioxide is deposited over the conductive lines 24 and the interwiring spaces 26 so as to form a dielectric liner 30. Subsequent to formation of the dielectric liner 30, spin on glass (SOG) 32 is deposited to fill the interwiring spaces and cured. After the SOG 32 is deposited, a capping layer 40 is deposited on the conductive pattern extending across the dielectric liner 30 and the interwiring spaces 26 which are filled with SOG. The capping layer 40 comprises a conventional dielectric material such as silicon dioxide.
Conventional semiconductors such as for example those fabricated according to the aforementioned method do not provide for sufficient insulation between the conductive lines 24 suitable for overcoming capacitive crosstalk in the case of closely separated conductive lines 24. Moreover, SOG materials have many drawbacks. When an SOG layer is formed to the thickness required of an interlevel dielectric, it exhibits an intolerable degree of cracking. In addition, adhesion failures are often observed at interfaces between SOG layers and metal interconnects. Delamination problems (i.e., adhesion failures at interfaces between SOG layers and overlying and underlying dielectric layers) have also been experienced.
In view of the above, there is a need in the art for a low dielectric constant material which may be employed to mitigate capacitive crosstalk between conductive lines of an integrated circuit, be less susceptible to cracking as compared to conventional materials and have good adhesion with an interface and/or conductive lines.